Conventional semiconductor devices are designed with a specific architecture. The architecture includes specific physical locations for corresponding portions, or components, of the semiconductor device. For example, in a semiconductor memory device, each gate, each memory cell and each transistor has a set physical location on the semiconductor device. Thus, during fabrication, each portion of the semiconductor device is to be formed in the corresponding physical location set by the design.
Although the semiconductor device is designed to be fabricated with certain components having set physical locations indicated by the architecture, one of ordinary skill in the art will readily recognize that the actual physical location may not match the designed physical location. Changes in the physical location of components in the semiconductor can occur for a variety of reasons. For example, the initial design may be changed, to accommodate new features or simplify fabrication. Often, these changes in design may not be reflected in documents relating to the architecture. However, these changes result in alterations in the physical locations of certain components of the semiconductor device.
In addition, failure analysis is often performed for semiconductor devices. Semiconductor devices may have failures, such as shorts or open circuits, that arise when the semiconductor device is fabricated. Similarly, components of the semiconductor devices may fail during testing and/or operation. As a result, it is desirable to perform failure analysis to determine the type of failure that has occurred, the components affected and the location of the failure.
In order to determine which component(s) of the semiconductor device have failed, the actual physical location of portions of the semiconductor device must be matched with the designed architecture of the semiconductor device. In other words, the architecture of the semiconductor device is physically verified in order to adequately perform failure analysis.
Currently, a scanning electron microscope (SEM) might be used for conventional physical verification of the architecture of a semiconductor device. The SEM would utilize voltage contrast generated by potential differences between conductors, typically metal layers, in the semiconductor device. However, one of ordinary skill in the art will readily recognize that a conventional SEM requires relatively close contact with conductors in order to obtain sufficient voltage contrast. If dielectric layers cover the conductive layers, the contrast in the image generated by the conventional SEM is weakened. As a result, the image from the conventional SEM may not adequately indicate the location of components of the semiconductor image. The poor contrast in the image may make it difficult or impossible to determine the physical location of components in the semiconductor device. It is possible to remove dielectric passivation layers, then use the conventional SEM to detect voltage contrast on the exposed top layer of the semiconductor device. However, one of ordinary skill in the art will realize that it may still not be possible to obtain sufficient contrast for lower layers of the device. In addition, removal of the dielectric layer(s) may adversely affect the performance of the device. If the device does not function, it may be impossible to generate the desired voltages in components of the device and, therefore, difficult or impossible to determine the locations of components in the semiconductor device. Consequently, physical verification of the architecture of the semiconductor device may be difficult or impossible using conventional techniques.
Accordingly, what is needed is a system and method for verifying the architecture of a semiconductor device. The present invention addresses such a need.